| CPC H02H 3/08 (2013.01) | 12 Claims |
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1. A shoot-through protection circuit comprising:
a first transistor switch comprising a first terminal connected to a positive bus, and a second terminal connected to a first center node via a first electrical path;
a second transistor switch comprising a first terminal connected to a negative bus, and a second terminal connected to the first center node via a second electrical path, wherein the first and second transistor switches are connected in series between the positive bus and the negative bus;
a circuitous third electrical path connecting the first center node to a first load output, the circuitous third electrical path being a path other than the first and second electrical paths; and
two magnetic cores, comprising:
a first magnetic core of the two magnetic cores through which the first electrical path and the circuitous third electrical path pass, the first magnetic core positioned along the first electrical path between the first transistor switch and the first center node; and
a second magnetic core of the two magnetic cores through which the second electrical path and the circuitous third electrical path pass, the second magnetic core positioned along the second electrical path between the first center node and the second transistor switch and being exclusive of the first magnetic core;
wherein a polarity of the first electrical path is aligned with a polarity of the circuitous third electrical path within the first magnetic core and a polarity of the second electrical path opposes the polarity of the circuitous third electrical path within the second magnetic core; and
wherein the circuitous third electrical path limits a rate at which current increases during a duration of a shoot-through event in which both the first transistor switch and second transistor switch are in a closed state.
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