| CPC H01L 33/62 (2013.01) [H01L 25/0753 (2013.01); H01L 33/54 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0066 (2013.01)] | 11 Claims |
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1. A component comprising a carrier and a plurality of semiconductor chips, wherein
the carrier has an electrically conductive carrier layer, wherein the carrier layer is embodied in structured fashion and has a plurality of partial layers spaced apart laterally,
the carrier has an encapsulation layer laterally enclosing the semiconductor chips, wherein the encapsulation layer is embodied in continuous fashion and thus holds together the laterally spaced apart partial layers of the carrier layer,
the encapsulation layer and the semiconductor chips, along the vertical direction perpendicular to a main surface of extent of the carrier or the carrier layer, terminate flush with one another,
the carrier layer has a mounting surface, on which the semiconductor chips are arranged, wherein the semiconductor chips are mechanically supported by the carrier layer and are electrically conductively connected to the partial layers,
the carrier has a common electrode for semiconductor chips of a group composed of a plurality of the semiconductor chips, wherein the common electrode is formed by one of the partial layers or by a plurality of partial layers—which are in electrical contact with one another—of the carrier layer,
the two adjacent partial layers of the carrier layer are spaced apart laterally from one another by an intermediate region, wherein
the two adjacent partial layers are assigned to different electrical polarities of the component,
the intermediate region has a lateral width that is at most 50 μm, and
one of the semiconductor chips is electrically conductively connected to the two adjacent partial layers, in plan view partly covers the two adjacent partial layers and bridges the associated intermediate region situated between the two adjacent partial layers.
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