US 12,278,291 B2
Thin film transistor array having a stacked multi-layer metal oxide channel formation region
Shunpei Yamazaki, Setagaya (JP); Kentaro Sugaya, Atsugi (JP); Ryota Hodo, Atsugi (JP); Kenichiro Makino, Ebina (JP); and Shuhei Nagatsuka, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/296,358
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Nov. 21, 2019, PCT No. PCT/IB2019/060011
§ 371(c)(1), (2) Date May 24, 2021,
PCT Pub. No. WO2020/115595, PCT Pub. Date Jun. 11, 2020.
Claims priority of application No. 2018-229973 (JP), filed on Dec. 7, 2018.
Prior Publication US 2022/0020881 A1, Jan. 20, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 21/308 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 21/308 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first insulating film;
a first oxide layer and a second oxide layer over and in contact with a top surface of the first insulating film;
a third oxide layer over and in contact with a top surface of the first oxide layer;
a fourth oxide layer over and in contact with a top surface of the second oxide layer;
a fifth oxide layer over and in contact with a top surface of the third oxide layer and a top surface of the fourth oxide layer;
a second insulating film over the fifth oxide layer; and
a conductive film over the second insulating film,
wherein the conductive film overlaps with the third oxide layer, the fourth oxide layer, and the first insulating film,
wherein the third oxide layer comprises a channel formation region of a first transistor,
wherein the fourth oxide layer comprises a channel formation region of a second transistor,
wherein the conductive film comprises a first region configured to function as a first gate electrode of the first transistor and a second region configured to function as a second gate electrode of the second transistor,
wherein, in a cross-sectional view in a channel width direction of the first transistor and the second transistor, the first insulating film comprises a region overlapping with the conductive film and being in contact with the second insulating film,
wherein the first insulating film has a first thickness in a region overlapping with the first oxide layer, a second thickness in a region overlapping with the second oxide layer, and a third thickness in a region not overlapping with the first oxide layer and the second oxide layer,
wherein the third thickness is smaller than the first thickness and the second thickness,
wherein, in a top view, the conductive film extends in a first direction, and
wherein, in the top view, the fifth oxide layer extends in the first direction.