US 12,278,289 B2
TMD inverted nanowire integration
Kevin P. O'Brien, Portland, OR (US); Carl Naylor, Portland, OR (US); Chelsey Dorow, Portland, OR (US); Kirby Maxey, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Ashish Verma Penumatcha, Beaverton, OR (US); Shriram Shivaraman, Hillsboro, OR (US); Chia-Ching Lin, Portland, OR (US); Sudarat Lee, Hillsboro, OR (US); and Uygar E. Avci, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 16, 2024, as Appl. No. 18/414,290.
Application 18/414,290 is a continuation of application No. 16/913,835, filed on Jun. 26, 2020, granted, now 11,935,956.
Prior Publication US 2024/0186416 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/7853 (2013.01) [H01L 29/0673 (2013.01); H01L 29/24 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6681 (2013.01); H01L 21/02568 (2013.01); H01L 21/0262 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a source contact;
a drain contact laterally spaced apart from the source contact; and
a semiconductor channel material layer laterally between the source contact and the drain contact, wherein the semiconductor channel material layer has a void therein in a channel region of the semiconductor channel material layer, and wherein the semiconductor channel material is above a top of the void, along sides of the void, and beneath a bottom of the void.