US 12,278,288 B2
Fin field-effect transistor device having hybrid work function layer stack
Chun-Neng Lin, Hsinchu (TW); Ming-Hsi Yeh, Hsinchu (TW); Hung-Chin Chung, Pingzhen (TW); and Hsin-Yun Hsu, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2024, as Appl. No. 18/673,615.
Application 18/673,615 is a division of application No. 18/357,794, filed on Jul. 24, 2023, granted, now 12,021,145.
Application 18/357,794 is a division of application No. 17/852,755, filed on Jun. 29, 2022, granted, now 12,051,753.
Application 17/852,755 is a division of application No. 16/528,031, filed on Jul. 31, 2019, granted, now 11,380,793, issued on Jul. 5, 2022.
Prior Publication US 2024/0313114 A1, Sep. 19, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first fin, a second fin, and a third fin protruding above a substrate, wherein the third fin is between the first fin and the second fin;
a gate dielectric layer over the first fin, the second fin, and the third fin;
a first work function layer over the gate dielectric layer, wherein the first work function layer extends along first sidewalls and a first upper surface of the first fin, and extends along a first sidewall of the third fin and a first portion of an upper surface of the third fin;
a second work function layer over the gate dielectric layer, wherein the second work function layer extends along second sidewalls and a second upper surface of the second fin, and extends along a second opposing sidewall of the third fin and a second portion of the upper surface of the third fin, wherein a third portion of the upper surface of the third fin is between the first portion and the second portion of the upper surface of the third fin, and is exposed by the first work function layer and the second work function layer; and
a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.