| CPC H01L 29/7827 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823412 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/124 (2013.01); H01L 29/42392 (2013.01); H01L 29/66666 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |

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1. A semiconductor device, comprising:
a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction that is perpendicular to an upper surface of the substrate;
a first gate structure surrounding the plurality of channel layers;
first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers, the first source/drain regions being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate;
an element isolation layer disposed on an upper portion of the first gate structure;
a semiconductor layer disposed on the element isolation layer, the semiconductor layer having a lower region having a planar upper surface and a vertical region protruding from the lower region in the first direction, and the semiconductor layer including second source/drain regions spaced apart from each other in the first direction;
a second gate structure disposed to surround a portion of the vertical region;
a first contact plug connected to one of the second source/drain regions by contacting the lower region; and
a second contact plug connected to other of the second source/drain regions by contacting the vertical region.
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