US 12,278,284 B2
Power semiconductor devices including a trenched gate and methods of forming such devices
Daniel Lichtenwalner, Raleigh, NC (US); Sei-Hyung Ryu, Cary, NC (US); Naeem Islam, Morrisville, NC (US); Woongsun Kim, Cary, NC (US); Matthew N. McCain, Raleigh, NC (US); and Joe McPherson, Plano, TX (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Mar. 24, 2023, as Appl. No. 18/125,779.
Application 18/125,779 is a continuation of application No. 17/080,956, filed on Oct. 27, 2020, granted, now 11,640,990.
Prior Publication US 2023/0231047 A1, Jul. 20, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 29/1608 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a trench in a semiconductor layer structure, the semiconductor layer structure having first and second major surfaces;
forming a bottom dielectric layer in the trench, wherein forming the bottom dielectric layer comprises forming and annealing a preliminary bottom dielectric layer;
forming a conformal gate dielectric layer in the trench directly on a center portion of the bottom dielectric layer;
forming the gate electrode in the trench on the gate dielectric layer,
forming a shield region in the drift layer underneath the trench.