US 12,278,279 B2
Semiconductor device
Takahiro Kato, Yokohama (JP); Tatsunori Sakano, Shinagawa (JP); Yusuke Kobayashi, Yokohama (JP); and Ryohei Gejo, Kawasaki (JP)
Assigned to KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Aug. 2, 2022, as Appl. No. 17/816,827.
Claims priority of application No. 2022-019264 (JP), filed on Feb. 10, 2022.
Prior Publication US 2023/0253485 A1, Aug. 10, 2023
Int. Cl. H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7397 (2013.01) [H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/41708 (2013.01); H01L 29/4238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first electrode;
a semiconductor member including a first semiconductor region being of a first conductive type, a second semiconductor region being of the first conductive type, a third semiconductor region being of a second conductive type, a fourth semiconductor region being of the second conductive type, a fifth semiconductor region being of the first conductive type, and a sixth semiconductor region being of the second conductive type, a position of the first semiconductor region in a first direction from the first electrode to the first semiconductor region being located between a position of the first electrode in the first direction and a position of the second semiconductor region in the first direction, the third semiconductor region including a first partial region and a second partial region, the second partial region being located between the first semiconductor region and the second semiconductor region in the first direction, at least a part of the fourth semiconductor region being located between the second partial region and the second semiconductor region in the first direction, the fifth semiconductor region being located between the second partial region and at least a part of the fourth semiconductor region in the first direction, The sixth semiconductor region being located between the first electrode and the first semiconductor region in the first direction;
a second electrode electrically connected to the second semiconductor region;
a third electrode, the first partial region being located between the first semiconductor region and the third electrode in the first direction, the third electrode overlapping the second semiconductor region, at least a part of the fourth semiconductor region, and the fifth semiconductor region in a second direction crossing the first direction;
a fourth electrode, the fourth electrode being located between the first partial region and the third electrode in the first direction, a direction from the fourth electrode to the second partial region being along the second direction; and
an insulating member, at least a part of the insulating member being provided between the semiconductor member and the third electrode, between the semiconductor member and the fourth electrode, and between the third electrode and the fourth electrode.