US 12,278,273 B2
Semiconductor device with backside gate isolation structure and method for forming the same
Huan-Chieh Su, Changhua County (TW); Chun-Yuan Chen, Hsinchu (TW); Li-Zhen Yu, New Taipei (TW); Lo-Heng Chang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/520,730.
Application 18/520,730 is a continuation of application No. 17/464,146, filed on Sep. 1, 2021, granted, now 11,901,428.
Claims priority of provisional application 63/151,405, filed on Feb. 19, 2021.
Prior Publication US 2024/0096996 A1, Mar. 21, 2024
Int. Cl. H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/823418 (2013.01); H01L 29/0649 (2013.01); H01L 29/0665 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first dielectric layer;
a stack of semiconductor layers disposed over the first dielectric layer;
a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction; and
a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure,
wherein the dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction,
wherein the isolation structure includes:
a second dielectric layer extending through the gate structure and the first dielectric layer, and
a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.