| CPC H01L 29/41775 (2013.01) [H01L 21/0254 (2013.01); H01L 21/32133 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01)] | 20 Claims |

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1. A method of forming a transistor device, comprising:
forming an isolation region within a substrate, wherein the isolation region wraps around an active area in a closed and unbroken loop in a plan view;
forming a source contact and a second source contact over the substrate;
forming a drain contact over the substrate;
forming a gate contact material over the substrate;
patterning the gate contact material to form a gate structure that wraps completely around the source contact along a continuous and unbroken path in the plan view and to form a separate second gate structure that wraps around a part of the second source contact in the plan view, wherein parts of the source contact, the second source contact, the drain contact, the gate structure, and the second gate structure are within the active area; and
wherein the gate structure has a different shape than the second gate structure, the second gate structure being open along a side facing away from the gate structure.
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