US 12,278,270 B2
Methods of manufacturing semiconductor devices
Massimo Camarda, Mascalucia (IT); and Ulrike Grossner, Villigen (CH)
Assigned to ETH Zuerich, Zurich (CH)
Appl. No. 17/776,311
Filed by ETH Zuerich, Zurich (CH)
PCT Filed Nov. 5, 2020, PCT No. PCT/EP2020/081051
§ 371(c)(1), (2) Date May 12, 2022,
PCT Pub. No. WO2021/094176, PCT Pub. Date May 20, 2021.
Claims priority of application No. 19208585 (EP), filed on Nov. 12, 2019.
Prior Publication US 2022/0399442 A1, Dec. 15, 2022
Int. Cl. H01L 29/16 (2006.01); H01L 21/3065 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/872 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 21/3065 (2013.01); H01L 29/0657 (2013.01); H01L 29/1606 (2013.01); H01L 29/2003 (2013.01); H01L 29/66053 (2013.01); H01L 29/872 (2013.01); H01L 29/66431 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming at least a part of a power semiconductor device, the method comprises:
homoepitaxially forming at least two silicon carbide (SiC) layers on a first side of a silicon carbide (SiC) substrate, wherein the at least two SiC layers include a first layer, hereinafter referred to as a buffer layer, on the first side of the silicon carbide substrate and having a same doping type as the silicon carbide substrate and a doping concentration being equal to or greater than 1017 cm−3 in order to increase a quality of at least one subsequent SiC layer, wherein the at least two SiC layers include a second layer, hereinafter referred to as an etch stopper layer, being deposited on the buffer layer and having a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process; and
forming a pattern of pits on a second side of the silicon carbide substrate, wherein the pattern of pits, being obtained by electrochemical etching, and extends at least completely thorough the silicon carbide substrate and the buffer layer.