US 12,278,268 B2
Semiconductor device
Kentaro Nasu, Kyoto (JP); and Takaaki Yoshioka, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/640,241
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Sep. 25, 2020, PCT No. PCT/JP2020/036385
§ 371(c)(1), (2) Date Mar. 3, 2022,
PCT Pub. No. WO2021/065740, PCT Pub. Date Apr. 8, 2021.
Claims priority of application No. 2019-180862 (JP), filed on Sep. 30, 2019.
Prior Publication US 2022/0344466 A1, Oct. 27, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0696 (2013.01) [H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor chip having a main surface;
a first conductivity type drift layer formed in a surface layer portion of the main surface;
a trench gate structure formed in the main surface such as to be in contact with the drift layer;
a second conductivity type channel region formed in the drift layer such as to cover a side wall of the trench gate structure; and
first and second source/drain regions formed at intervals in a region along the side wall of the trench gate structure in the drift layer such as to oppose each other across the channel region, wherein the channel region further covers a bottom wall of the trench gate structure.