| CPC H01L 27/14634 (2013.01) [H01L 24/08 (2013.01); H01L 27/14623 (2013.01); H01L 27/14636 (2013.01); H01L 2224/08145 (2013.01)] | 20 Claims |
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1. An image sensor, comprising:
a logic chip, the logic chip including:
a lower substrate,
a lower bonding layer on the lower substrate, and
a lower wiring layer between the lower substrate and the lower bonding layer, the lower bonding layer including:
a lower dielectric layer,
a lower conductive pad and a lower shield structure, each of which penetrates the lower dielectric layer, the lower conductive pad and the lower shield structure being spaced apart from each other, and
a lower wiring line which penetrates the lower dielectric layer and electrically connects the lower conductive pad to the lower shield structure, wherein the lower wiring line, the lower conductive pad, and the lower shield structure are integrally formed into a first single body; and
a sensor chip stacked on the logic chip, the sensor chip including:
an upper substrate,
an upper bonding layer below the upper substrate, the upper bonding layer and the lower bonding layer being in contact with each other, and the upper bonding layer including:
an upper dielectric layer,
an upper conductive pad and an upper shield structure, each of which penetrates the upper dielectric layer, the upper conductive pad and the upper shield structure being spaced apart from each other, and
an upper wiring line which penetrates the upper dielectric layer and electrically connects the upper conductive pad to the upper shield structure,
wherein the upper wiring line, the upper conductive pad, and the upper shield structure are integrally formed into a second single body, and
an upper wiring layer between the upper substrate and the upper bonding layer,
wherein the upper conductive pad and the lower conductive pad overlap and contact each other, and the upper wiring line and the lower wiring line overlap and contact each other.
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