US 12,278,247 B2
Signal processing device having photodiode
Tomoya Sasago, Kanagawa (JP); Shintaro Maekawa, Kanagawa (JP); Yu Maehashi, Tokyo (JP); and Yasuharu Ota, Tokyo (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Nov. 20, 2023, as Appl. No. 18/514,601.
Application 18/514,601 is a continuation of application No. 17/578,001, filed on Jan. 18, 2022, granted, now 11,855,106.
Claims priority of application No. 2021-008584 (JP), filed on Jan. 22, 2021; and application No. 2021-171595 (JP), filed on Oct. 20, 2021.
Prior Publication US 2024/0088174 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); G01S 7/48 (2006.01); H01L 31/0203 (2014.01); H01L 31/107 (2006.01); H04N 25/77 (2023.01)
CPC H01L 27/14603 (2013.01) [H01L 27/14643 (2013.01); H04N 25/77 (2023.01)] 14 Claims
OG exemplary drawing
 
1. A signal processing device comprising:
a plurality of pixel signal processing units arranged in a first direction and a second direction, each of the plurality of signal processing units acquiring a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode; and
a signal line group arranged corresponding to the plurality of pixel signal processing units arranged in the first direction and including a signal line to which a plurality of signals corresponding to a plurality of bits of digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are output in common,
wherein each of the plurality of pixel signal processing units includes a counter circuit that acquires the digital signal by counting the number of pulses output from a corresponding avalanche photodiode and an output circuit that reads a value of each of the plurality of bits from the counter circuit and outputs the read values to the signal line, and
wherein the signal line and a wiring through which a signal output from the counter circuit passes before being input to the output circuit are arranged in different layers each other.