US 12,278,243 B2
Semiconductor apparatus having expansion wires for electrically connecting chips
Chenyang Zhang, Beijing (CN); Fuqiang Li, Beijing (CN); Xue Dong, Beijing (CN); Meili Wang, Beijing (CN); Xuan Liang, Beijing (CN); Fei Wang, Beijing (CN); Mingxing Wang, Beijing (CN); Zhanfeng Cao, Beijing (CN); Yanling Han, Beijing (CN); and Xinxin Zhao, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Nov. 18, 2021, as Appl. No. 17/529,969.
Claims priority of application No. 202110273812.3 (CN), filed on Mar. 12, 2021.
Prior Publication US 2022/0293635 A1, Sep. 15, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 25/075 (2006.01); H01L 33/62 (2010.01)
CPC H01L 27/124 (2013.01) [H01L 27/1292 (2013.01); H01L 25/0753 (2013.01); H01L 33/62 (2013.01); H01L 2933/0066 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor apparatus, comprising:
a base substrate;
a plurality of chips arranged on the base substrate, wherein each of the plurality of chips comprises a chip main body and a plurality of terminals arranged on the chip main body;
a plurality of fixed connection portions arranged on the base substrate, wherein the plurality of fixed connection portions are arranged adjacent to the plurality of chips, respectively;
a terminal expansion layer arranged on the base substrate, wherein the terminal expansion layer comprises a conductive material; and
a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are configured to electrically connect the plurality of chips,
wherein each of the plurality of expansion wires comprises at least one first wire segment and a second wire segment, and each of the at least one first wire segment is configured to electrically connect a terminal of one of two chips among the plurality of chips and one fixed connection portion of the plurality of fixed connection portions adjacent to the one of the two chips among the plurality of chips, and the second wire segment is configured to connect two fixed connection portions among the plurality of fixed connection portions between the two chips among the plurality of chips,
wherein the plurality of terminals comprise at least a first terminal and a second terminal, and two of the plurality of expansion wires are configured to electrically connect the two chips among the plurality of chips;
wherein one of the two of the plurality of expansion wires is configured to electrically connect respective first terminals of the two chips, and the other of the two of the plurality of expansion wires is configured to electrically connect respective second terminals of the two chips; and
wherein the one of the two of the plurality of expansion wires configured to electrically connect the respective first terminals of the two chips comprises the second wire segment parallel to the second wire segment comprised in the other of the two of the plurality of expansion wires configured to electrically connect the respective second terminals of the two chips, and/or
the one of the two of the plurality of expansion wires configured to electrically connect the respective first terminals of the two chips comprises the second wire segment having a length equal to a length of the second wire segment comprised in the other of the two of the plurality of expansion wires configured to electrically connect the respective second terminals of the two chips.