US 12,278,242 B2
Array substrate, display panel, and manufacturing method of array substrate
Yang Liu, Shenzhen (CN); Deyan Li, Shenzhen (CN); and Jun Yi, Shenzhen (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/296,233
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Apr. 23, 2021, PCT No. PCT/CN2021/089326
§ 371(c)(1), (2) Date Oct. 20, 2022,
PCT Pub. No. WO2022/217639, PCT Pub. Date Oct. 20, 2022.
Claims priority of application No. 202110397636.4 (CN), filed on Apr. 14, 2021.
Prior Publication US 2024/0030227 A1, Jan. 25, 2024
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/124 (2013.01) [G02F 1/136222 (2021.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1255 (2013.01); H01L 27/1262 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate;
a thin film transistor layer disposed on the substrate, wherein the thin film transistor layer comprises a thin film transistor assembly, the thin film transistor assembly comprises at least one thin film transistor, and the thin film transistor is electrically connected to a first conductive layer;
a passivation layer disposed on the thin film transistor layer, wherein the passivation layer comprises a thin film transistor region corresponding to the thin film transistor, and the passivation layer is provided with a first via hole and a second via hole in the thin film transistor region;
a pixel electrode layer disposed on the passivation layer, wherein the pixel electrode layer comprises a pixel electrode connected to the first conductive layer through the first via hole and the second via hole; and
a color filter layer disposed on the pixel electrode layer, wherein the color filter layer is provided with an opening, the first via hole corresponds to the opening, and the second via hole is staggered from the opening.