US 12,278,240 B2
IC logic device, layout, system, and method
I-Wen Wang, Hsinchu (TW); Chia-Chun Wu, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Yung-Chen Chien, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); and Xiangdong Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 20, 2022, as Appl. No. 17/750,168.
Claims priority of provisional application 63/310,478, filed on Feb. 15, 2022.
Prior Publication US 2023/0261002 A1, Aug. 17, 2023
Int. Cl. H01L 27/00 (2006.01); H01L 27/118 (2006.01); G06F 30/392 (2020.01)
CPC H01L 27/11807 (2013.01) [G06F 30/392 (2020.01); H01L 2027/11881 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
first and second power rails extending in a first direction, wherein each of the first and second power rails is configured to carry one of a power supply voltage or a power supply reference voltage;
a third power rail extending in the first direction between the first and second power rails, wherein the third power rail is configured to carry the other of the power supply voltage or the power supply reference voltage; and
a plurality of transistors comprising:
first through fourth active areas extending in the first direction between the first and second power rails, wherein each of the second and third active areas is adjacent to the third power rail;
a plurality of gate structures extending in a second direction perpendicular to the first direction; and
first and second conductive segments extending in the second direction across the third power rail, wherein each of the first and second conductive segments is electrically connected to a first set of source/drain (S/D) structures in each of the second and third active areas,
wherein the plurality of transistors is configured as one of an and-or-inverter (AOI), an or-and-inverter (OAI), or a four-input NAND gate.