| CPC H01L 27/11807 (2013.01) [H03K 3/0372 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01)] | 11 Claims |
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1. A semiconductor integrated circuit comprising:
an output circuit configured to output a predetermined differential signal from a positive output terminal and a negative output terminal;
a first logic circuit including a first plurality of PMOS transistors and a first plurality of NMOS transistors, respective gates of the first plurality of PMOS transistors being arranged in a predetermined direction, respective gates of the first plurality of NMOS transistors being arranged in the predetermined direction;
a second logic circuit including a second plurality of PMOS transistors and a second plurality of NMOS transistors, respective gates of the second plurality of PMOS transistors being arranged in the predetermined direction and respective gates of the second plurality of NMOS transistors being arranged in the predetermined direction;
a positive signal line wired along the predetermined direction from the positive output terminal and connecting the respective gates of each of the first and second plurality of PMOS transistors to the positive output terminal; and
a negative signal line wired along the predetermined direction from the negative output terminal and connecting the respective gates of each of the first and second plurality of NMOS transistors to the negative output terminal, wherein
the output circuit, the first logic circuit, and the second logic circuit are respectively arranged in a first row, a second row and a third row of a gate wiring layer, the second row being adjacent to the first row, and the third row being adjacent to the second row,
the positive signal line and the negative signal line are gate layer wiring including segments extending linearly across and intersecting with all of the first row, the second row, and the third row of the gate wiring layer,
the output circuit includes an inverter circuit including a third PMOS transistor and a third NMOS transistor, and
the positive signal line is connected to the respective gates of the third PMOS transistor and the third NMOS transistor of the inverter circuit,
wherein, in the first logic circuit, an output data line has a first branch extending in the predetermined direction to be connected to a first PMOS transistor included in the first plurality of PMOS transistors and a second branch extending in a direction perpendicular to the predetermined direction to be connected to a first NMOS transistor included in the first plurality of NMOS transistors, and
the second branch of the output data line is wired around a portion of the positive signal line and a portion of the negative signal line such that the output data line is not linearly wired in the first logic circuit.
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