US 12,278,237 B2
Stacked FETS with non-shared work function metals
Ruilong Xie, Niskayuna, NY (US); Julien Frougier, Albany, NY (US); Junli Wang, Slingerlands, NY (US); Dechao Guo, Niskayuna, NY (US); Ruqiang Bao, Niskayuna, NY (US); Rishikesh Krishnan, Cohoes, NY (US); and Balasubramanian S. Pranatharthiharan, Santa Clara, CA (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 8, 2021, as Appl. No. 17/545,610.
Prior Publication US 2023/0178553 A1, Jun. 8, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/0259 (2013.01); H01L 21/28088 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 23/5286 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first field effect transistor (FET) device stacked over a second FET device, wherein the first FET device comprises a first functional gate structure containing a first work function metal and the second FET device comprises a second functional gate structure containing a second work function metal;
a stacked device separating dielectric material layer located between the first FET device and the second FET device;
a first gate cut dielectric structure located laterally adjacent to the first FET device; and
a second gate cut dielectric structure located laterally adjacent to the second FET device, wherein a portion of the first gate cut dielectric structure passes through an opening in the stacked device separating dielectric material layer and is present laterally adjacent to the second FET device, and wherein the portion of the first gate cut dielectric structure that passes through the opening has an enlarged width as compared to a width of a portion of the first gate cut dielectric structure that does not pass through the opening.