US 12,278,236 B2
Semiconductor device with helmet structure between two semiconductor fins
Kuo-Cheng Ching, Hsinchu County (TW); Shi-Ning Ju, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 16, 2024, as Appl. No. 18/444,356.
Application 18/444,356 is a division of application No. 17/866,365, filed on Jul. 15, 2022, granted, now 11,942,476.
Application 17/007,786 is a division of application No. 16/103,721, filed on Aug. 14, 2018, granted, now 10,763,255, issued on Sep. 1, 2020.
Application 17/866,365 is a continuation of application No. 17/007,786, filed on Aug. 31, 2020, granted, now 11,393,814, issued on Jul. 19, 2022.
Prior Publication US 2024/0194675 A1, Jun. 13, 2024
Int. Cl. H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/0228 (2013.01); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/31053 (2013.01); H01L 21/32139 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductive fin;
a second semiconductive fin;
a first dielectric layer laterally between the first and second semiconductive fins, wherein from a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile;
a first gate structure extending across the first and second semiconductive fins and the first dielectric layer;
a spacer layer underlying the first dielectric layer and further extending to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin; and
an oxide material nested in the first dielectric layer, wherein a top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.