US 12,278,230 B2
Method of manufacturing conductors for semiconductor device
Kam-Tou Sio, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); Hui-Ting Yang, Hsinchu (TW); Shun Li Chen, Hsinchu (TW); Ko-Bin Kao, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Ru-Gun Liu, Hsinchu (TW); and Charles Chew-Yuen Young, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 26, 2023, as Appl. No. 18/341,369.
Application 17/225,664 is a division of application No. 16/544,373, filed on Aug. 19, 2019, granted, now 10,978,439, issued on Apr. 13, 2021.
Application 16/544,373 is a division of application No. 15/676,225, filed on Aug. 14, 2017, granted, now 10,388,644, issued on Aug. 20, 2019.
Application 18/341,369 is a continuation of application No. 17/225,664, filed on Apr. 8, 2021, granted, now 11,688,730.
Claims priority of provisional application 62/427,570, filed on Nov. 29, 2016.
Prior Publication US 2023/0335545 A1, Oct. 19, 2023
Int. Cl. H01L 27/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01)
CPC H01L 27/0207 (2013.01) [H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 21/823437 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing conductors for a semiconductor device, the method comprising:
forming active regions (ARs) in a first layer, the ARs extending in a first direction;
forming a conductive layer over the first layer;
forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other;
removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and
selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.