US 12,278,229 B2
Hybrid manufacturing for integrated circuit devices and assemblies
Wilfred Gomes, Portland, OR (US); Abhishek A. Sharma, Portland, OR (US); Mauro J. Kobrinsky, Portland, OR (US); and Doug B. Ingerly, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/474,275.
Application 18/474,275 is a continuation of application No. 17/114,700, filed on Dec. 8, 2020, granted, now 11,817,442.
Prior Publication US 2024/0030213 A1, Jan. 25, 2024
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08501 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32501 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01007 (2013.01); H01L 2924/01014 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a first IC structure having a first face and a second face;
a second IC structure having a first face and a second face, wherein the first face of the second IC structure is at least partially between the second face of the first IC structure and the second face of the second IC structure, and wherein the second face of the first IC structure is closer to the first face of the second IC structure than the first face of the first IC structure;
an IC component having a first face and a second face, wherein the first face of the first IC structure is coupled to the second face of the IC component by interconnects, and wherein the first face of the first IC structure is at least partially between the second face of the IC component and the second face of the first IC structure;
a bonding interface between the second face of the first IC structure and the first face of the second IC structure; and
a conductive via having at least a portion in the first IC structure, at least a portion in the second IC structure, and extending through the bonding interface,
wherein a surface area of the first face of the second IC structure is different from a surface area of the second face of the first IC structure.