| CPC H01L 25/167 (2013.01) [H01L 21/4857 (2013.01); H01L 23/053 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 2224/29099 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48158 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85399 (2013.01); H01L 2224/92247 (2013.01)] | 17 Claims |
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1. A manufacturing method of a hybrid embedded packaging structure, comprising:
manufacturing a substrate, wherein the substrate comprises a first insulating layer, a conductive copper column penetrating through the first insulating layer, a chip-embedded cavity formed in the first insulating layer and a first circuit layer electrically connected with the conductive copper column;
arranging a supporting member on a bottom of the substrate, wherein the supporting member is configured for pre-fixing an electronic device assembly;
pre-fixing the electronic device assembly on an inner side of the supporting member corresponding to the chip-embedded cavity, wherein the electronic device assembly comprises a first electronic device and a second electronic device, the second electronic device is arranged on a back surface of the first electronic device, a terminal surface of the first electronic device faces the supporting member, and a terminal surface of the second electronic device faces away from the first electronic device;
packaging the electronic device assembly, with a part of the first circuit layer and a terminal of the second electronic device exposed to form a second insulating layer;
removing the supporting member;
manufacturing a second circuit layer on the bottom of the substrate; and
performing wire bonding to connect the terminal of the second electronic device with the first circuit layer, wherein manufacturing the substrate comprises:
preparing a bearing plate, wherein the bearing plate sequentially comprises a core layer, a first metal layer, a second metal layer, an etching barrier layer and a first metal seed layer from bottom to top;
manufacturing a first photoresist layer on a surface of the first metal seed layer, wherein the first photoresist layer is provided with a conductive copper column window and a sacrificial copper column window;
respectively manufacturing a conductive copper column and a sacrificial copper column at positions corresponding to the conductive copper column window and the sacrificial copper column window;
removing the first photoresist layer;
forming the first insulating layer by laminating which covers the copper columns and is thinned to exposed end portions of the conductive copper column and the sacrificial copper column;
manufacturing a second metal seed layer on a surface where the copper columns are exposed;
forming a second photoresist layer by applying a photoresist material on a surface of the second metal seed layer, exposing and developing the photoresist material, and manufacturing a first circuit layer pattern;
electroplating a circuit, and removing the second photoresist layer and an exposed part of the second metal seed layer to form the first circuit layer;
splitting the first metal layer from the second metal layer;
removing the second metal layer, the etching barrier layer and the first metal seed layer;
applying photoresist materials on both sides, exposing and developing the photoresist materials to form a third photoresist layer and a fourth photoresist layer, with the first circuit layer and the conductive copper column being covered and the sacrificial copper column being exposed; and
removing the sacrificial copper column to form the chip-embedded cavity.
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