US 12,278,222 B2
Method of fabricating semiconductor package including sub-interposer substrates
Yanggyoo Jung, Suwon-si (KR); Chulwoo Kim, Suwon-si (KR); Hyo-Chang Ryu, Suwon-si (KR); and Yun Seok Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 21, 2023, as Appl. No. 18/338,372.
Application 18/338,372 is a continuation of application No. 17/396,308, filed on Aug. 6, 2021, granted, now 11,721,679.
Application 17/396,308 is a continuation of application No. 16/583,051, filed on Sep. 25, 2019, granted, now 11,145,637, issued on Oct. 12, 2021.
Claims priority of application No. 10-2019-0034502 (KR), filed on Mar. 26, 2019.
Prior Publication US 2023/0335540 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/16 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/528 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/95001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor package, comprising:
providing a first sub-interposer substrate, which includes a first base layer and an interconnection pattern provided in the first base layer, the interconnection pattern horizontally-extending in the first base layer;
forming an integrated device, which is buried in the first sub-interposer substrate;
forming a second sub-interposer substrate, which includes a second base layer and a through electrode formed in the second base layer;
disposing the second sub-interposer substrate on the first sub-interposer substrate to bring surfaces of the first base layer and the second base layer into contact with each other;
mounting a semiconductor chip on the second sub-interposer substrate; and
mounting the first sub-interposer substrate on a package substrate.