US 12,278,217 B2
Backside integrated voltage regulator for integrated circuits
Namhoon Kim, San Jose, CA (US); Woon-Seong Kwon, Santa Clara, CA (US); Houle Gan, Santa Clara, CA (US); Yujeong Shim, Cupertino, CA (US); Mikhail Popovich, Danville, CA (US); and Teckgyu Kang, Saratoga, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Sep. 3, 2024, as Appl. No. 18/823,093.
Application 18/239,368 is a division of application No. 17/667,104, filed on Feb. 8, 2022, granted, now 11,830,855, issued on Nov. 28, 2023.
Application 18/823,093 is a continuation of application No. 18/239,368, filed on Aug. 29, 2023.
Application 17/667,104 is a continuation of application No. 16/788,994, filed on Feb. 12, 2020, granted, now 11,276,668, issued on Mar. 15, 2022.
Prior Publication US 2025/0006706 A1, Jan. 2, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 49/02 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 28/10 (2013.01); H01L 28/40 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package comprising:
an IC die including a silicon layer; and
an integrated power regulator configured to provide power to the IC die, the integrated power regulator being positioned adjacent to the silicon layer and connected to the silicon layer via an intervening power distribution network (PDN).