US 12,278,216 B2
3D semiconductor device and structure with metal layers
Zvi Or-Bach, Haifa (IL); and Brian Cronquist, Klamath Falls, OR (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on May 19, 2024, as Appl. No. 18/668,221.
Application 18/668,221 is a continuation of application No. 18/604,695, filed on Mar. 14, 2024, granted, now 12,051,674.
Application 18/604,695 is a continuation in part of application No. 18/395,546, filed on Dec. 23, 2023, granted, now 11,961,827, issued on Apr. 16, 2024.
Application 18/395,546 is a continuation in part of application No. 18/236,325, filed on Aug. 21, 2023, granted, now 11,916,045, issued on Feb. 27, 2024.
Application 18/236,325 is a continuation in part of application No. 18/214,524, filed on Jun. 27, 2023, granted, now 11,967,583, issued on Apr. 23, 2024.
Application 18/214,524 is a continuation in part of application No. 18/141,415, filed on Apr. 29, 2023, granted, now 11,784,169, issued on Oct. 10, 2023.
Application 18/141,415 is a continuation in part of application No. 18/105,826, filed on Feb. 4, 2023, granted, now 11,676,945, issued on Jun. 13, 2023.
Application 18/105,826 is a continuation in part of application No. 17/986,831, filed on Nov. 14, 2022, granted, now 11,605,616, issued on Mar. 14, 2023.
Application 17/986,831 is a continuation in part of application No. 17/882,607, filed on Aug. 8, 2022, granted, now 11,532,599, issued on Dec. 20, 2022.
Application 17/882,607 is a continuation in part of application No. 17/750,338, filed on May 21, 2022, granted, now 11,450,646, issued on Sep. 20, 2022.
Application 17/750,338 is a continuation in part of application No. 17/680,297, filed on Feb. 25, 2022, granted, now 11,424,222, issued on Aug. 23, 2022.
Application 17/680,297 is a continuation in part of application No. 17/536,019, filed on Nov. 27, 2021, granted, now 11,309,292, issued on Apr. 19, 2022.
Application 17/536,019 is a continuation in part of application No. 17/334,928, filed on May 31, 2021, granted, now 11,217,565, issued on Apr. 19, 2022.
Application 17/334,928 is a continuation in part of application No. 17/195,517, filed on Mar. 8, 2021, granted, now 11,063,024, issued on Jul. 13, 2021.
Application 17/195,517 is a continuation in part of application No. 17/020,766, filed on Sep. 14, 2020, granted, now 11,018,116, issued on May 25, 2021.
Application 17/020,766 is a continuation in part of application No. 16/683,244, filed on Nov. 13, 2019, granted, now 10,811,395, issued on Oct. 20, 2020.
Application 16/683,244 is a continuation in part of application No. 16/409,840, filed on May 12, 2019, granted, now 10,515,935, issued on Dec. 24, 2019.
Application 16/409,840 is a continuation in part of application No. 15/990,684, filed on May 28, 2018, granted, now 10,297,580, issued on May 21, 2019.
Application 15/990,684 is a continuation in part of application No. 15/721,955, filed on Oct. 1, 2017, granted, now 10,014,282, issued on Jul. 3, 2018.
Application 15/721,955 is a continuation in part of application No. 15/008,444, filed on Jan. 28, 2016, granted, now 9,786,636, issued on Oct. 10, 2017.
Application 15/008,444 is a continuation in part of application No. 14/541,452, filed on Nov. 14, 2014, granted, now 9,252,134, issued on Feb. 2, 2016.
Application 14/541,452 is a continuation of application No. 14/198,041, filed on Mar. 5, 2014, granted, now 8,921,970, issued on Dec. 30, 2014.
Application 14/198,041 is a continuation of application No. 13/726,091, filed on Dec. 22, 2012, granted, now 8,674,470, issued on Mar. 18, 2014.
Prior Publication US 2024/0321832 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/743 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/522 (2013.01); H01L 24/25 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 29/66621 (2013.01); H01L 27/092 (2013.01); H01L 29/4236 (2013.01); H01L 29/78 (2013.01); H01L 2224/24146 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/01104 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising formation of first control circuits;
a second metal layer overlaying said at least one first metal layer;
a second level overlaying said second metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said first control circuits comprise at least one sense amplifier,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said control circuits, and
wherein said first control circuits are connected to control data written to at least one of said second memory cells;
a third metal layer disposed above said third level; and
a fourth metal layer disposed above said third metal layer;
wherein said second transistors comprise second transistor gate locations,
wherein said third transistors comprise third transistors gate locations,
wherein said third transistor gate locations are aligned to said second transistor gate locations within less than 100 nm but more than 0.2 nm alignment error, being formed following two independently aligned lithography steps,
wherein at least one of said second transistors comprises a metal gate,
wherein said fourth metal layer has an average thickness which is at least twice an average thickness of said second metal layer,
wherein said fourth metal layer comprises a global power distribution grid,
wherein said second transistors comprise second gate lines,
wherein said third transistors comprise third gate lines, and
wherein said second gate lines and said third gate lines were deposited in the same process step.