US 12,278,214 B2
Integrated circuit package and method
Chen-Hua Yu, Hsinchu (TW); Chuei-Tang Wang, Taichung (TW); Chieh-Yen Chen, Taipei (TW); and Wei Ling Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,442.
Application 17/873,442 is a division of application No. 16/684,913, filed on Nov. 15, 2019, granted, now 11,621,244.
Prior Publication US 2022/0359467 A1, Nov. 10, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 21/4857 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first die array comprising first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array;
a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar;
a second die array comprising second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and
a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.