	US 12,278,209 B2
	Peripheral circuit having recess gate transistors and method for forming the same
Yanwei Shi, Wuhan (CN); Yanhong Wang, Wuhan (CN); Cheng Gan, Wuhan (CN); Liang Chen, Wuhan (CN); Wei Liu, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Kun Zhang, Wuhan (CN); and Yuancheng Yang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 26, 2021, as Appl. No. 17/510,779.
Application 17/510,779 is a continuation of application No. PCT/CN2021/103560, filed on Jun. 30, 2021.
Prior Publication US 2023/0005875 A1, Jan. 5, 2023
Int. Cl. H01L 25/065 (2023.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01)

CPC H01L 24/80 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/41 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)]

20 Claims

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming, on a first substrate, a first semiconductor structure comprising an array of NAND memory strings;

forming, on a second substrate, a second semiconductor structure comprising a recess gate transistor and a flat gate transistor, the recess gate transistor comprising a recess gate structure protruding into the second substrate, and a gate length of the flat gate transistor being greater than a gate length of the recess gate transistor in a plan view; and

bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.