	US 12,278,204 B2
	Pattern decomposition lithography techniques
Charles H. Wallace, Portland, OR (US); Hossam A. Abdallah, Portland, OR (US); Elliot N. Tan, Portland, OR (US); Swaminathan Sivakumar, Portland, OR (US); Oleg Golonzka, Beaverton, OR (US); and Robert M. Bigwood, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 17, 2021, as Appl. No. 17/404,870.
Application 15/419,147 is a division of application No. 13/976,082, granted, now 9,558,947, issued on Jan. 31, 2017, previously published as PCT/US2011/067930, filed on Dec. 29, 2011.
Application 17/404,870 is a continuation of application No. 16/692,589, filed on Nov. 22, 2019, granted, now 11,107,786.
Application 16/692,589 is a continuation of application No. 15/475,793, filed on Mar. 31, 2017, granted, now 10,490,519, issued on Nov. 26, 2019.
Application 15/475,793 is a continuation of application No. 15/419,147, filed on Jan. 30, 2017, granted, now 10,409,152, issued on Sep. 10, 2019.
Prior Publication US 2021/0375807 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G03F 7/16 (2006.01); G03F 1/36 (2012.01); G03F 1/50 (2012.01); G03F 1/70 (2012.01); G03F 7/00 (2006.01); G03F 7/40 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/263 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01)

CPC H01L 24/09 (2013.01) [G03F 1/36 (2013.01); G03F 1/50 (2013.01); G03F 1/70 (2013.01); G03F 7/0035 (2013.01); G03F 7/16 (2013.01); G03F 7/40 (2013.01); G03F 7/70741 (2013.01); H01L 21/02345 (2013.01); H01L 21/0273 (2013.01); H01L 21/0274 (2013.01); H01L 21/2633 (2013.01); H01L 21/30604 (2013.01); H01L 21/3086 (2013.01); H01L 27/0207 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08053 (2013.01); H01L 2224/0912 (2013.01); H01L 2924/14 (2013.01)]

15 Claims

1. An integrated circuit structure, comprising:

a substrate;

a plurality of gate structures above the substrate, the plurality of gate structures comprising:

unidirectional linear gate structures aligned in a first direction, the unidirectional linear gate structures including a first group of unidirectional linear gate structures, each linear gate structure of the first group having a first width and aligned in the first direction, and a second group of unidirectional linear gate structures, each linear gate structure of the second group having a second width and aligned in the first direction, the second width different than the first width; and

wherein the linear gate structures of the first group are arranged in an interleaved fashion with the linear gate structures of the second group in a series that alternates between a linear gate structure of the first group and a linear gate structure of the second group, the series traversing the layer in a second direction perpendicular to the first direction as seen in a plan view of the layer of the unidirectional linear gate structures.