US 12,278,203 B2
Semiconductor structure and manufacturing method thereof
Chen-Yu Tsai, Taoyuan (TW); Ku-Feng Yang, Hsinchu County (TW); Tsang-Jiuh Wu, Hsinchu (TW); and Wen-Chih Chiou, Miaoli County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 16, 2022, as Appl. No. 17/841,686.
Prior Publication US 2023/0411326 A1, Dec. 21, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 2224/08111 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first die;
a second die stacked on the first die, wherein the second die has a dielectric portion disposed on the first die and a semiconductor material portion disposed on the dielectric portion;
a smoothing layer, disposed on the first die and disposed around the second die, wherein the smoothing layer comprises a first dielectric layer disposed on the first die and a second dielectric layer disposed on the first dielectric layer; and
a filling material layer, disposed on the smoothing layer and around the second die, wherein the smoothing layer surrounds the dielectric portion, sidewalls of the dielectric portion are isolated from the filling material layer by the smoothing layer, and the semiconductor material portion is surrounded and covered by the filling material layer, and
a material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.