| CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
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1. A non-volatile memory device comprising:
a first structure;
a second structure; and
a connection layer,
wherein the first structure comprises: a first substrate; a peripheral circuit disposed on the first substrate; a first insulation structure disposed on the first substrate; a plurality of first bonding pads disposed on the first insulation structure; and a first interconnect structure surrounded by the first insulation structure, wherein the first interconnect structure electrically connects the peripheral circuit to the first bonding pads;
wherein the second structure comprises: a conductive etch stop layer; a common source line layer disposed on the conductive etch stop layer; a stacked structure including a plurality of gate layers and a plurality of interlayer insulation layers, wherein gate layers of the plurality of gate layers are alternately stacked with interlayer insulation layers of the plurality of interlayer insulation layers on the common source line layer; a plurality of channel structures penetrating through a cell region of the stacked structure and contacting the common source line layer; a second insulation structure disposed on the stacked structure; a plurality of second bonding pads disposed on the second insulation structure; and a second interconnect structure surrounded by the second insulation structure, wherein the second interconnect structure electrically connects the gate layers and the channel structures to the second bonding pads, wherein the second insulation structure contacts the first insulation structure, wherein the second bonding pads contact the first bonding pads, respectively, and wherein the second structure is bonded to the first structure;
wherein the connection layer comprises: a third insulation structure disposed on the second structure and covering the conductive etch stop layer and the second insulation structure; an input/output via penetrating through the third insulation structure and connected to the second interconnect structure; and an input/output pad connected to the input/output via and disposed on the third insulation structure, and
wherein an interface between the second insulation structure and the third insulation structure is located at a vertical level between a top surface and a bottom surface of the conductive etch stop layer.
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