a first chip package comprising a semiconductor integrated-circuit (IC) chip, a first sealing layer in a space at a same horizontal level as the semiconductor integrated-circuit (IC) chip and beyond a sidewall of the semiconductor integrated-circuit (IC) chip, a first metal interconnect vertically in the first sealing layer, a first interconnection scheme under the semiconductor integrated-circuit (IC) chip, first sealing layer and first metal interconnect and coupling the semiconductor integrated-circuit (IC) chip to the first metal interconnect, and a first metal bump under and coupling to the first interconnection scheme and at a bottom of the first chip package, wherein the semiconductor integrated-circuit (IC) chip comprises a plurality of first volatile memory cells configured for storing first data therein, a second and a third metal interconnect and a switch coupling to the second and third metal interconnects, wherein the switch is configured, in accordance with the first data, to control coupling between the second and third metal interconnects through the switch; and

a second chip package over and coupling to the first chip package, wherein the second chip package comprises a non-volatile memory (NVM) integrated-circuit (IC) chip configured for storing second data therein associated with the first data and a second interconnection scheme under and coupling to the non-volatile memory (NVM) integrated-circuit (IC) chip, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip couples to the semiconductor integrated-circuit (IC) chip through, in sequence, the second interconnection scheme, first metal interconnect and first interconnection scheme.