US 12,278,191 B2
Semiconductor packages having wiring patterns
Youngchan Ko, Seoul (KR); Myungsam Kang, Hwaseong-si (KR); Jeongseok Kim, Cheonan-si (KR); and Bongju Cho, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 19, 2022, as Appl. No. 17/723,689.
Claims priority of application No. 10-2021-0143530 (KR), filed on Oct. 26, 2021.
Prior Publication US 2023/0131240 A1, Apr. 27, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 25/105 (2013.01); H01L 23/5389 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/182 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lower redistribution structure comprising a wiring layer, and a via connected to the wiring layer;
a semiconductor chip on the lower redistribution structure;
wiring patterns on the lower redistribution structure, the wiring patterns comprising a first wiring pattern;
metal patterns on the wiring patterns, the metal patterns comprising a first connection pillar and a first dummy pillar on the first wiring pattern;
an encapsulant on the lower redistribution structure, the semiconductor chip, the wiring patterns, and the metal patterns; and
an upper redistribution structure on the encapsulant,
wherein the first connection pillar is directly connected to the upper redistribution structure, and
wherein the first wiring pattern comprises pad portions, and a line portion interconnecting the pad portions.