| CPC H01L 23/535 (2013.01) [H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/32134 (2013.01); H01L 21/76805 (2013.01); H01L 21/7684 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 23/481 (2013.01); H01L 29/45 (2013.01)] | 20 Claims |
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1. An interconnect structure disposed in a dielectric layer and connected to a device of an integrated circuit, the interconnect structure comprising:
a first bulk metal layer;
a barrier layer disposed between the first bulk metal layer and the dielectric layer;
a second bulk metal layer disposed over and physically contacting the first bulk metal layer, wherein the second bulk metal layer has a first bulk portion disposed over a second bulk portion, the first bulk portion physically contacts the dielectric layer, and the barrier layer is further disposed between the second bulk portion and the dielectric layer;
a first interface between the first bulk metal layer and a bottom of the second bulk metal layer along a first direction, wherein the first interface is substantially planar; and
a second interface between the first bulk metal layer and the bottom of the second bulk metal layer along a second direction, wherein the second direction is different than the first direction and the second interface is substantially curved.
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10. A semiconductor structure comprising:
a first dielectric layer;
a first contact etch stop layer (CESL) disposed over the first dielectric layer;
a second dielectric layer disposed over the first CESL;
a second CESL disposed over the second dielectric layer;
a third dielectric layer disposed over the second CESL;
a gate interconnect connected to a gate stack, wherein the gate interconnect extends from a top of the third dielectric layer through the third dielectric layer, the second CESL, the second dielectric layer, and the first CESL to the gate stack; and
a source/drain interconnect connected to a source/drain, wherein the source/drain interconnect extends from the top of the third dielectric layer through the third dielectric layer, the second CESL, the second dielectric layer, the first CESL, and the first dielectric layer to the source/drain, wherein:
the gate interconnect includes a first bulk layer disposed over a first barrier layer, wherein the first barrier layer is disposed between sidewalls of the first bulk layer and the third dielectric layer, the second CESL, the second dielectric layer, and the first CESL, and
the source/drain interconnect includes a second bulk layer, a third bulk layer, and a second barrier layer, wherein:
the second bulk layer is disposed over the third bulk layer;
the second barrier layer is disposed between sidewalls of the third bulk layer and the second dielectric layer, the first CESL, and the first dielectric layer; and
the second barrier layer is disposed between sidewalls of the second bulk layer and the second dielectric layer but not the sidewalls of the second bulk layer and the third dielectric layer and the second CESL.
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17. A semiconductor structure comprising:
a first dielectric layer, a contact etch stop layer disposed over the first dielectric layer, and a second dielectric layer disposed over the contact etch stop layer;
a source/drain contact disposed in the first dielectric layer, wherein the source/drain contact is connected to a source/drain, the source/drain contact has a first metal layer and a first glue layer, and the first glue layer wraps the first metal layer;
a gate via disposed in the second dielectric layer, the contact etch stop layer, and the first dielectric layer, wherein the gate via is connected to a gate stack, the gate via has a second metal layer and a second glue layer, and the second glue layer wraps the second metal layer; and
a source/drain via disposed in the second dielectric layer, the contact etch stop layer, and the first dielectric layer, wherein the source/drain via has a third metal layer, the first glue layer is between sidewalls of the third metal layer and the first dielectric layer, and the sidewalls of the third metal layer physically contact the contact etch stop layer and the second dielectric layer.
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