US 12,278,187 B1
Integrated structure having a P-type semiconductor diffusion barrier layer forming a Van Der Waals junction with a P-type substrate and electronic device including the same
Jun Hong Park, Jinju-si (KR); Do Hyeon Lee, Jinju-si (KR); and Su Yeon Cho, Ulsan (KR)
Assigned to INDUSTRY-ACADEMIC COOPERATION FOUNDATION GYEONGSANG NATIONAL UNIVERSITY, Jinju-si (KR)
Filed by INDUSTRY-ACADEMIC COOPERATION FOUNDATION GYEONGSANG NATIONAL UNIVERSITY, Jinju-si (KR)
Filed on Nov. 1, 2024, as Appl. No. 18/934,307.
Claims priority of application No. 10-2023-0151913 (KR), filed on Nov. 6, 2023.
Int. Cl. H10D 64/64 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/53266 (2013.01) [H01L 21/02568 (2013.01); H01L 21/28537 (2013.01); H01L 23/5283 (2013.01); H10D 64/64 (2025.01); H10D 64/647 (2025.01)] 9 Claims
OG exemplary drawing
 
1. An integrated structure comprising:
a P-type silicon substrate or P-type silicon-on-insulator (SOI) substrate;
a conductive layer spaced apart from the substrate and including a metal or a metal compound; and
a diffusion barrier layer provided between the substrate and the conductive layer and includes a P-type semiconductor material, wherein
the substrate and the diffusion barrier layer directly contact and form a van der Waals junction, and
the diffusion barrier layer blocks the injection of electrons from the substrate to the conductive layer and performs the injection of holes from the conductive layer to the substrate.