US 12,278,184 B2
Vertically-stacked field effect transistor cell
Albert M Chu, Nashua, NH (US); Junli Wang, Slingerlands, NY (US); Albert M. Young, Fishkill, NY (US); and Dechao Guo, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Mar. 31, 2022, as Appl. No. 17/657,378.
Prior Publication US 2023/0317611 A1, Oct. 5, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/5286 (2013.01) [H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a top transistor device stacked on a bottom transistor device;
a via in direct contact with a source drain of the top transistor device and a source drain of the bottom transistor device; and
a top contact directly contacting the source drain of the top transistor device.