laterally-spaced memory blocks individually comprising a vertical stack of alternating insulative tiers and conductive tiers, and channel-material strings of memory cells in the vertical stack;

intervening material laterally-between and longitudinally-along the immediately-laterally-adjacent memory blocks, the intervening material extending upwardly from an uppermost of the alternating insulative and conductive tiers to a respective top surface of the intervening material between the memory blocks;

conductive vias in each of the laterally-spaced memory-block regions, wherein the conductive vias are formed in insulating material that is directly above the channel material strings, individual of the conductive vias being directly electrically coupled to individual of the channel-material strings, the conductive vias having respective top surfaces; and

a horizontally-elongated isolation trench formed in a top part of the stack within each of the laterally-spaced memory-block regions, wherein the horizontally-elongated isolation trench is in parallel with the intervening material and positioned above a dummy structure, and wherein laterally-spaced select gates that extend laterally to the intervening material are formed on opposite sides of the isolation trench, and

wherein the top surfaces of the conductive vias, and the respective top surface of the intervening material not being horizontally planar and formed through the insulating material, only a portion of the respective intervening-material-top-surfaces being elevationally-coincident with at least a portion of the respective conductive-via-top surfaces.