| CPC H01L 23/5256 (2013.01) [H01L 23/5283 (2013.01); H10D 62/151 (2025.01); H10D 64/258 (2025.01); H10D 64/512 (2025.01); H10D 84/0133 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] | 4 Claims |
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1. A semiconductor structure, comprising:
a substrate, including an active area and an isolation surrounding the active area, wherein the isolation is downwardly extended from a top surface of the substrate;
a transistor, disposed on the top surface of the substrate and in the active area;
a first conductive trench structure, downwardly extended from the top surface of the substrate and between a gate structure of the transistor and the isolation;
a second conductive trench structure downwardly extended from the top surface of the substrate and disposed adjacent to the transistor opposite to the first conductive trench structure, wherein a depth of the each of the first conductive trench structure and the second conductive trench structure is less than a depth of the isolation; and
a contact, disposed on the top surface of the substrate and between the first conductive trench structure and the second conductive trench structure, wherein the contact is in contact with the transistor;
wherein at least one of the first conductive trench structure and the second conductive trench structure is disposed in a peripheral region of a chip.
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