| CPC H01L 23/5228 (2013.01) [H01C 7/006 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76877 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H10D 1/474 (2025.01); H10D 1/692 (2025.01)] | 17 Claims |
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1. A semiconductor device manufacturing method, the method comprising:
forming a lower metal layer, a barrier metal layer, a dielectric layer and a metal nitride layer, sequentially, on a substrate;
performing etching the metal nitride layer, thereby forming a first metal nitride, a second metal nitride;
forming a hard mask layer directly disposed on the first metal nitride, the second metal nitride and the dielectric layer, the hard mask layer comprising an insulating layer;
performing etching the hard mask layer, the dielectric layer, the barrier metal layer and the lower metal layer to form a metal/insulator/metal (MIM) capacitor and a thin film resistor (TFR), the MIM capacitor comprising a first hard mask, the first metal nitride, a first dielectric layer, a first barrier metal and a first lower metal, and the thin film resistor comprising a second hard mask, the second metal nitride, a second dielectric layer, a second barrier metal and a second lower metal;
forming an inter-metal dielectric layer to cover the MIM capacitor and the thin film resistor; and
forming a plurality of vias in the inter-metal dielectric layer, the plurality of vias comprising:
a first via connecting the first barrier metal and forming through the first hard mask and the first dielectric layer in the MIM capacitor;
a second via connecting the first metal nitride and forming through the first hard mask in the MIM capacitor; and
a third via connecting the second metal nitride and forming through the second hard mask in the TFR,
wherein the first metal nitride is enclosed by the first hard mask and the first dielectric layer.
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