US 12,278,176 B2
Integrated circuit structure and method for forming the same
Yi-Wen Pan, New Taipei (TW); and Chung-Chi Ko, Nantou County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Oct. 1, 2021, as Appl. No. 17/492,423.
Claims priority of provisional application 63/185,084, filed on May 6, 2021.
Prior Publication US 2022/0359376 A1, Nov. 10, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76819 (2013.01); H01L 21/76829 (2013.01); H01L 21/76831 (2013.01); H01L 23/5283 (2013.01); H01L 29/41725 (2013.01); H01L 29/4232 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a transistor over a substrate;
forming an interlayer dielectric (ILD) layer over the transistor;
depositing a metal layer over the ILD layer;
patterning the metal layer to form a metal feature;
depositing a low-k dielectric layer over the ILD layer and the metal feature;
etching back the low-k dielectric layer to lower a top surface of the low-k dielectric layer to a position lower than a top surface of the metal feature;
depositing a dielectric layer over the low-k dielectric layer and the metal feature; and
performing a first CMP process to the dielectric layer until the metal feature is exposed.