US 12,278,168 B1
Semiconductor device including interconnect structure with planarization stop layer
Joongsuk Oh, Watervliet, NY (US); Jaemyung Choi, Niskayuna, NY (US); and Kang-Ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 16, 2024, as Appl. No. 18/886,289.
Claims priority of provisional application 63/569,548, filed on Mar. 25, 2024.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 29/417 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76819 (2013.01); H01L 21/76885 (2013.01); H01L 21/76892 (2013.01); H01L 23/562 (2013.01); H01L 29/41725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a base layer and an interconnect structure on the base layer, the interconnect structure comprising:
a 1st metal line on the base layer;
a 1st top via vertically protruded from the 1st metal line without a connection surface therebetween;
an isolation layer on the 1st metal line and the 1st top via; and
a planarization stop layer vertically and laterally on the isolation layer.