| CPC H01L 23/481 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/02183 (2013.01); H01L 21/76898 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08148 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] | 20 Claims |

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1. A method, comprising:
providing a first workpiece that includes:
a first substrate comprising a logic transistor, and
a first interconnect structure disposed on a frontside of the first substrate;
providing a second workpiece that includes:
a second substrate comprising a memory device,
a second interconnect structure disposed on a frontside of the second substrate, and
a through via extending through a portion of the second substrate and a portion of the second interconnect structure;
forming a first bonding layer on the first interconnect structure;
forming a second bonding layer on the second interconnect structure;
bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer;
thinning the second substrate;
forming a protective film over the thinned second substrate;
forming a backside via opening through the protective film and the thinned second substrate to expose the through via; and
forming a backside through via in the backside via opening to physically couple to the through via.
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