| CPC H01L 23/481 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor storage device, comprising:
a first structure including a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure; and
a second structure on the first structure, said second structure comprising:
a stack structure including gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction;
a plate layer, which extends on the stack structure and covers at least a portion of an upper surface of the stack structure;
channel structures, which penetrate at least partially through the stack structure, said channel structures respectively including a channel layer extending in the vertical direction and connected to the plate layer, a gate dielectric layer surrounding an outer side surface of the channel layer, and a core insulating layer covering an inner side surface of the channel layer;
separation regions, which penetrate at least partially through the stack structure, extend in a first direction, and separate the gate electrodes in a second direction perpendicular to the first direction; and
upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads;
wherein based on an upper surface of the substrate, an upper surface of the channel layer and an upper surface of the gate dielectric layer are in contact with the plate layer, on a level higher than an uppermost gate electrode, among the gate electrodes; and
wherein the second structure further includes a base layer, which comprises a semiconductor material, extends between the plate layer and the stack structure, and at least partially surrounds an outer side surface of the gate dielectric layer.
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