US 12,278,153 B2
Semiconductor device with cushion structure and method for fabricating the same
Tse-Yao Huang, Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jun. 12, 2023, as Appl. No. 18/208,466.
Application 18/208,466 is a division of application No. 17/882,541, filed on Aug. 6, 2022.
Prior Publication US 2024/0047287 A1, Feb. 8, 2024
Int. Cl. H01L 23/18 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/18 (2013.01) [H01L 21/76837 (2013.01); H01L 23/5226 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising a circuit area and a non-circuit area next to the circuit area, wherein the circuit area and the non-circuit area are side-by-side to each other;
a top dielectric layer positioned on the substrate;
a top interconnector positioned along the top dielectric layer and above the circuit area;
a cushion structure positioned along the top dielectric layer and above the non-circuit area;
a top conductive pad positioned on the top interconnector;
a bottom passivation layer comprising:
a recessing portion positioned on the top dielectric layer, surrounding the top conductive pad, and covering the cushion structure; and
a plurality of protruding portions positioned on the recessing portion, covering a portion of the top conductive pad, and above the circuit area;
a redistribution layer positioned on the top conductive pad, covering the plurality of protruding portions, and extending from the circuit area to the non-circuit area to cover a portion of the recessing portion; and
an external connector positioned on the redistribution layer and above the cushion structure; wherein the cushion structure comprises a porous polymeric material, wherein the cushion structure is made of an energy-removable material and is positioned directly below the external connector for providing a cushion effect for the external connector;
wherein the top interconnector comprises:
a filler layer positioned along the top dielectric layer and electrically coupling to the top conductive pad;
an isolation layer positioned between the filler layer and the top dielectric layer; and
a barrier layer positioned between the filler layer and the isolation layer;
wherein the top interconnector comprises an adhesive layer positioned between the filler layer and the barrier layer;
wherein the top interconnector comprises a seed layer positioned between the filler layer and the adhesive layer;
wherein a top surface of the recessing portion and a top surface of the top conductive pad are at the same vertical level, such that a bottom surface of the redistribution layer is at the same vertical level of the top surface of the recessing portion.