US 12,278,149 B2
Through-substrate via test structure
Chun-Lin Lu, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Apr. 13, 2022, as Appl. No. 17/719,400.
Claims priority of application No. 111108657 (TW), filed on Mar. 9, 2022.
Prior Publication US 2023/0290695 A1, Sep. 14, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/66 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 23/481 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A through-substrate via (TSV) test structure, comprising:
a substrate comprising a test region;
a first TSV located in the substrate of the test region; and
a test device located on the substrate of the test region, wherein the test device and the first TSV are separated from each other, and a shortest distance between the test device and the first TSV is less than 10 μm, wherein
the substrate comprises a scribe line region and a chip region, and
there is no conductive component between the first TSV and the test device.