US 12,278,146 B2
Fin field-effect transistor device and method of forming the same
Che-Yu Lin, Hsinchu (TW); Chien-Wei Lee, Kaohsiung (TW); Chien-Hung Chen, Hsinchu (TW); Wen-Chu Hsiao, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/064,764.
Application 18/064,764 is a continuation of application No. 17/169,090, filed on Feb. 5, 2021, granted, now 11,527,442.
Application 17/169,090 is a continuation of application No. 16/430,177, filed on Jun. 3, 2019, granted, now 11,088,028, issued on Aug. 10, 2021.
Claims priority of provisional application 62/773,909, filed on Nov. 30, 2018.
Prior Publication US 2023/0103483 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/02068 (2013.01); H01L 21/3065 (2013.01); H01L 21/823437 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a recess in a fin and adjacent to a gate structure;
performing a wet etch process to clean the recess;
treating the recess with a plasma process, wherein the plasma process removes a material of the fin exposed by the recess at a first etch rate along a depth direction of the recess, and simultaneously removes the material of the fin exposed by the recess at a second etch rate along a lateral direction of the recess, wherein the first etch rate is lower than the second etch rate; and
forming a source/drain region in the recess.