CPC H01L 21/823418 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method comprising:
forming an opening through a multilayer stack and into a substrate;
depositing a barrier layer at a bottom of the opening, wherein after the depositing the barrier layer a top level of the barrier layer is below a bottom of the multilayer stack, wherein the barrier layer is meniscus shaped, wherein the depositing the barrier layer comprises performing a bottom-up deposition of an undoped silicon material, and wherein the bottom-up deposition is performed until the barrier layer has a first thickness adjacent to a bottom of the opening and a second thickness different from the first thickness, the second thickness being adjacent to a sidewall of the substrate, and wherein a ratio of the second thickness to the first thickness is between about 1:1 and about 1:10;
forming a multilayer source/drain region over the barrier layer by depositing a first semiconductor material over the barrier layer; and
forming a stack of nanostructures by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.
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