US 12,278,142 B2
Method for manfacturing semiconductor device for reducing partcle-induced defects
Li-Han Lin, Taoyuan (TW); and Jr-Chiuan Wang, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 11, 2022, as Appl. No. 17/741,589.
Prior Publication US 2023/0369104 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01)
CPC H01L 21/76826 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
forming a first insulating layer over a substrate;
forming a conductive contact in the first insulating layer;
forming a second insulating layer having an opening on the first insulating layer, the opening exposing a top surface of the conductive contact;
forming a conductive line structure in the opening of the second insulating layer, the conductive line structure covering a portion of the exposed top surface of the conductive contact thereby forming a contact void between the second insulating layer and the conductive line structure;
forming a plasma oxide layer to cover exposed surfaces of the conductive line structure, the second insulating layer, and the conductive contact;
performing a wet cleaning process by using an aqueous solution containing negatively charged ions;
forming a capping layer over the plasma oxide layer, the capping layer filling the contact void; and
performing an etching back process to remove the capping layer above the contact void.