CPC H01L 21/76826 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01)] | 14 Claims |
1. A method for manufacturing a semiconductor structure, comprising:
forming a first insulating layer over a substrate;
forming a conductive contact in the first insulating layer;
forming a second insulating layer having an opening on the first insulating layer, the opening exposing a top surface of the conductive contact;
forming a conductive line structure in the opening of the second insulating layer, the conductive line structure covering a portion of the exposed top surface of the conductive contact thereby forming a contact void between the second insulating layer and the conductive line structure;
forming a plasma oxide layer to cover exposed surfaces of the conductive line structure, the second insulating layer, and the conductive contact;
performing a wet cleaning process by using an aqueous solution containing negatively charged ions;
forming a capping layer over the plasma oxide layer, the capping layer filling the contact void; and
performing an etching back process to remove the capping layer above the contact void.
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