US 12,278,137 B2
Manufacturing method of semiconductor structure and semiconductor structure
Zhugen Chu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 8, 2021, as Appl. No. 17/453,881.
Application 17/453,881 is a continuation of application No. PCT/CN2021/111882, filed on Aug. 10, 2021.
Claims priority of application No. 202110212376.9 (CN), filed on Feb. 25, 2021.
Prior Publication US 2022/0270916 A1, Aug. 25, 2022
Int. Cl. H01L 21/762 (2006.01); H10D 62/10 (2025.01)
CPC H01L 21/76224 (2013.01) [H10D 62/115 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein a capacitor functional structure layer is formed on a surface of the substrate, and particles exist on the surface of the capacitor functional structure layer;
forming a first dielectric layer on the surface of the substrate, wherein the first dielectric layer covers the capacitor functional structure layer;
grinding to remove part of the first dielectric layer until the particles are exposed, and removing the particles, to form first recesses on a surface of the remaining first dielectric layer; and
depositing a silicon precursor on the surface of the first dielectric layer at a first deposition rate to form a first dielectric material layer, wherein the first dielectric material layer fills the first recesses;
depositing the silicon precursor on a surface of the first dielectric material layer at a second deposition rate to form a second dielectric material layer, wherein the second deposition rate is greater than the first deposition rate; and
grinding to remove part of the second dielectric material layer, such that the first dielectric material layer and the remaining second dielectric material layer together form a second dielectric layer, wherein the second dielectric layer fills the first recesses.