US 12,278,123 B2
Semiconductor processing apparatus
Jingfeng Wei, Beijing (CN); and Qing She, Beijing (CN)
Assigned to BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
Appl. No. 17/918,077
Filed by BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
PCT Filed Apr. 1, 2021, PCT No. PCT/CN2021/084860
§ 371(c)(1), (2) Date Oct. 10, 2022,
PCT Pub. No. WO2021/204050, PCT Pub. Date Oct. 14, 2021.
Claims priority of application No. 202020527685.6 (CN), filed on Apr. 10, 2020.
Prior Publication US 2023/0162998 A1, May 25, 2023
Int. Cl. H01L 21/67 (2006.01); C23C 16/54 (2006.01); H01L 21/677 (2006.01)
CPC H01L 21/67167 (2013.01) [C23C 16/54 (2013.01); H01L 21/67184 (2013.01); H01L 21/67201 (2013.01); H01L 21/67742 (2013.01); H01L 21/67769 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor processing apparatus, configured to process a wafer, comprising:
a vacuum interlock chamber;
a plurality of apparatus bodies, one apparatus body of the plurality of apparatus bodies including a transfer platform, and at least two reaction chambers being arranged along a circumferential direction of the transfer platform; and
a temporary storage channel, any two neighboring apparatus bodies of the plurality of apparatus bodies being communicated through the temporary storage channel, and the temporary storage channel being configured to temporarily store the wafer,
wherein the transfer platform is configured to transfer the wafer between the vacuum interlock chamber and the at least two reaction chambers, between the temporary storage channel and the vacuum interlock chamber, and between the temporary storage channel and the at least two reaction chambers, and
wherein the plurality of apparatus bodies includes:
a first apparatus body connected to the vacuum interlock chamber, a shape of the transfer platform of the first apparatus body being a regular quadrilateral; and
a second apparatus body, a shape of the transfer platform of the second apparatus body being a regular pentagon.